A. Field of the Invention
The present invention relates to a semiconductor device and semiconductor device manufacturing method.
B. Description of the Related Art
Rectifier diodes utilizing a silicon (Si) semiconductor p-n junction are known. In particular, high speed recovery diodes in which reverse recovery time is improved are widely used in high frequency switching applications. A diode is configured of a p-type anode layer, an n+ type cathode layer, and an n− type drift layer provided between the p-type anode layer and n+ type cathode layer in order to maintain high breakdown voltage, and exhibits rectifying characteristics using a p-n junction of the p-type anode layer and n− type drift layer.
As the n− type drift layer has an impurity concentration lower than that of the p-type anode layer or n+ type cathode layer, it is also called an i-type layer (intrinsic region). As impurities introduced into each silicon layer configuring the diode, mainly boron (B) or the like is used in the p-type anode layer, mainly phosphorus (P) or the like is used in the n− type drift layer, and phosphorus, arsenic (As), antimony (Sb), or the like, is used in the n+ type cathode layer.
Furthermore, a method is known in which a recombination center is formed by a transition metal such as gold (Au), platinum (Pt), or iron (Fe) being introduced into the n− type drift layer, thereby controlling the lifetime of the minority carriers. This method accelerates the reverse recovery characteristics of the diode. Another method is known in which lifetime is controlled by irradiating with a light element such as proton (H+) or helium (He), thereby generating defects in the silicon layer. These methods are useful as methods of carrying out localized lifetime control.
Also, the following method has been proposed as a method of forming a diode p-n junction without implementing a heretofore known diffusion method using boron. An n-type semiconductor layer with a low impurity concentration is epitaxially grown on an n-type semiconductor substrate, an oxide film of a desired pattern is formed on the surface of the n-type semiconductor layer, and an active region edge portion and guard ring region are formed by ion implantation, with the oxide film as a mask. Further, the portion in which the active region is formed is exposed, a paste containing platinum is applied to the back surface of the semiconductor substrate in this condition, and the platinum is thermally diffused. In this way the vicinity of the surface of the semiconductor layer active region is inverted to p-type, whereby an inversion region is shallowly formed (for example, refer to JP-A-2002-231968).
A description will be given of a heretofore known diode structure. FIG. 19 is a sectional view showing a heretofore known diode structure. As shown in FIG. 19, p-type inversion region 103 is shallowly formed below a region of a surface of n− type drift layer 102 not covered with oxide film 105. P-type inversion region 103 is formed by n− type drift layer 102 inverting to p-type due to high concentration platinum accumulated in a region in the vicinity of the surface of n− type drift layer 102.
A p-type anode region is configured of p-type inversion region 103. In FIG. 19, the interface of the region in which the conductivity type is inverted by the diffusion of platinum is shown by a broken line (the same also applies in other drawings). The interface shown by the broken line is p-n junction portion 108 of p-type inversion region 103 and n− type drift layer 102. Reference signs 101, 104, 106, and 107 in FIG. 19 are an n+ type semiconductor substrate that forms an n+ type cathode layer, a p-type guard ring region, an anode electrode, and a cathode electrode.
A description will be given, referring to FIGS. 20 to 22, of a method of manufacturing the diode shown in FIG. 19. FIGS. 20 to 22 are sectional views showing conditions partway through the manufacture of the heretofore known diode. Firstly, oxide film 105 is formed by thermal oxidation on the surface of n− type drift layer 102 deposited on n+ type semiconductor substrate 101. Next, a portion of oxide film 105 corresponding to the region in which p-type guard ring region 104 is to be formed is removed. Next, with the remaining portion of oxide film 105 as a mask, boron is ion implanted into n− type drift layer 102. The condition thus far is shown in FIG. 20.
Next, heat treatment is carried out at a temperature of 1,000° C. or more, thereby forming p-type guard ring region 104. At this time, the silicon surface is covered with oxide film 105. Next, a portion of oxide film 105 corresponding to the region in which an active region is to be formed is removed. In this condition, silica paste 110 containing platinum is applied to the back surface of n+ type semiconductor substrate 101, and the platinum is thermally diffused by heat treatment at about of 900° C. The condition thus far is shown in FIG. 21. Because of this, the vicinity of the surface of n− type drift layer 102 active region is inverted to p-type, whereby p-type inversion region 103 is formed. The condition thus far is shown in FIG. 22. Subsequently, anode electrode 106 and cathode electrode 107 are formed, thereby completing the diode and reaching the condition shown in FIG. 19.
It is known that the platinum diffused in n+ type semiconductor substrate 101 and n− type drift layer 102 has a U-shaped impurity concentration distribution eccentrically located at a high concentration at the silicon surface (for example, refer to JP-A-2009-239269). The high concentration platinum eccentrically located at n− type drift layer 102 surface acts as an acceptor, compensating the impurity concentration in the vicinity of the surface of n− type drift layer 102. Because of this, the vicinity of the surface of n− type drift layer 102 active region is inverted to p-type, whereby p-type inversion region 103 is formed. The diode shown in FIG. 19 is such that p-type inversion region 103 is utilized as a p-type anode region.
The heretofore described diode manufacturing method is such that, by the n-type impurity concentration in the vicinity of the surface of n− type drift layer 102 being compensated by the platinum that has been formed into an acceptor, p-n junction portion 108 of p-type inversion region 103 and n− type drift layer 102 is formed. Because of this, variation occurs in the platinum concentration distribution in the silicon layer after platinum diffusion due to variation in the platinum diffusion conditions, and there is a tendency for the junction depth of p-n junction portion 108 and the carrier concentration distribution of p-type inversion region 103 to be unstable.
Also, p-type inversion region 103 formed by the platinum being formed into an acceptor has a shallow diffusion depth compared with that of a p-type diffusion region formed by a p-type impurity such as boron being diffused, and the p-type impurity concentration also tends to be low. Because of this, the electrical field intensity of the p-type anode region formed of p-type inversion region 103 in the vicinity of an aperture end portion of p-n junction portion 108 increases when there is reverse bias, and there is concern that the breakdown voltage will decrease noticeably.
A method including a step of introducing point defects into one main surface of a semiconductor substrate, and a step of the electrical activation of a transition metal being advanced by the point defects by the transition metal being introduced from the one main surface or other main surface of the semiconductor substrate after the point defect introduction step, has been proposed as a method of eliminating this kind of problem (for example, refer to JP-A-2012-38810).
Furthermore, a method whereby the curvature radius of the end portion of the p-type inversion region is increased and the electrical field concentration in the end portion of the p-type inversion region alleviated by the end portion form after patterning of a dielectric forming a mask for selectively introducing the transition metal being tapered by damaging the surface of the dielectric, thereby controlling the intake of platinum into the oxide film, is proposed in JP-A-2012-38810. Also, JP-A-2012-38810 discloses that the process can be shortened by the p-type regions of the active region and termination structure region both being formed in the platinum diffusion step.
A description will be given of another example of a method of manufacturing the heretofore known diode. FIGS. 23 to 27 are sectional views showing another example of conditions partway through the manufacture of the heretofore known diode. FIGS. 23 to 27 are FIG. 10 of JP-A-2012-38810. Firstly, oxide film 116 is formed on n− type drift layer 112 deposited on the front surface of n+ type semiconductor substrate 111. Next, oxide film 116 surface is damaged using plasma treatment. The condition thus far is shown in FIG. 23.
Next, oxide film 116 is selectively removed by etching. Because of this, the end portion form of oxide film 116 after patterning is a tapered form that widens from the upper surface side toward n− type drift layer 112 side. Next, with the remaining portion of oxide film 116 as a mask, a boron ion implantation is carried out from n− type drift layer 112 surface, thus selectively introducing point defects into the vicinity of the surface of n− type drift layer 112. The condition thus far is shown in FIG. 24. Next, silica paste 120 containing platinum is applied to the back surface of n+ type semiconductor substrate 111, and the platinum is thermally diffused at a temperature of in the region of 900° C. The condition thus far is shown in FIG. 25.
The formation of the platinum into an acceptor is advanced by the point defects introduced into n− type drift layer 112, and p-type inversion region 113 is stably formed only in an exposed region of n− type drift layer 112 not covered with oxide film 116. The condition thus far is shown in FIG. 26. Subsequently, anode electrode 117 and cathode electrode 118 are formed, thereby completing the diode and reaching the condition shown in FIG. 27. Reference signs 114 and 115 in FIG. 26 are a p-type guard ring region and a p-type channel stopper region.
As a method of controlling the platinum concentration distribution, JP-A-2009-239269 discloses a method whereby the platinum concentration distribution is controlled by the vacancy density in the silicon substrate being controlled by heat treatment at a temperature of 1,150° C. or more, and the platinum being diffused into vacancies introduced into the silicon substrate.
Also, another method has been proposed in which a heavy metal is diffused in a semiconductor substrate and then a low-lifetime predetermined region is provided in the semiconductor substrate by the interior of the semiconductor substrate being irradiated with charged particles, and heat treatment at 650° C. or more is performed (for example, refer to JP-A-2003-282575). In JP-A-2003-282575, crystal defects are locally formed by helium irradiation at an arbitrary depth in the silicon layer, and the platinum concentration is locally increased by the platinum being moved by heat treatment into a region in which the helium is eccentrically located.
A method also has been proposed that includes a heavy metal diffusion step of diffusing a heavy metal into a semiconductor substrate from one surface of the semiconductor substrate, a masking step of protecting a desired region of the surface of the semiconductor substrate after the diffusion, an electron beam irradiation step of irradiating with an electron beam from the surface side after protecting the region, and a heat treatment step of carrying out heat treatment at 650° C. or more after the electron beam irradiation (for example, refer to Japanese Patent No. 3,952,452). In Japanese Patent No. 3,952,452, the platinum concentration distribution is controlled by the electron beam irradiation and heat treatment being carried out after the platinum diffusion. By disposing a mask that controls the electron dose on the silicon surface at this time, the platinum concentration distribution is formed in the element plane.
A method also has been proposed that includes a step of attaching or diffusing an impurity element onto or into a semiconductor substrate, and a step of irradiating the semiconductor substrate with charged particles of a light element, forming a getter layer in a region in the semiconductor substrate in which the charged particles stop, and causing the impurity element to concentrate in the getter layer by subjecting the semiconductor substrate to heat treatment, thereby forming a low-lifetime layer (for example, refer to JP-A-4-125933). In JP-A-4-125933, the platinum in the semiconductor substrate is disposed again by the proton irradiation and heat treatment being carried out after the platinum diffusion, thereby controlling the platinum concentration distribution.
The following method also has been proposed. Firstly, prior to diffusing a heavy metal in a semiconductor wafer, an inert element Ar is implanted into the semiconductor wafer. The Ar implantation is carried out from the semiconductor wafer surface above the position in the semiconductor wafer in which a p-n junction is formed. Subsequently, a heavy metal diffusion is carried out (for example, refer to JP-A-2008-4704). In JP-A-2008-4704, the platinum is evenly diffused by Ar being implanted into the silicon surface before the platinum diffusion.
Another method has been proposed in which a level due to platinum is formed in a proton irradiation position by carrying out proton irradiation and heat treatment after a diffusion of platinum from platinum silicide (for example, refer to D. Hu et al, “Effect of Proton Irradiation Dose on the Gettering Efficiency of Platinum and the Performance of Local Lifetime-Controlled Power Diodes” (Japan Journal of Applied Physics, 2007, Volume 46, Issue 2, Pages 566 to 568)). It also has been proposed that recovery characteristics are changed by carrying out a helium or proton irradiation on a diode into which platinum or palladium (Pd) has been introduced as a lifetime killer (for example, refer to J. Vobecky et al “The Radiation Enhanced Diffusion (RED) Diode Realization of a Large Area p+p−n−n+ Structure with High SOA” (IEEE 21st International Symposium on Power Semiconductor Devices & IC's 2009: ISPSD 2009 (Barcelona), June, 2009, Pages 144 to 147) and J. Vobecky et al “Fast Recovery Radiation Enhanced Diffusion (RED) Diode: Palladium versus Platinum” (13th European Conference on Power Electronics and Applications 2009: EPE 2009 (Barcelona), October 2009, Pages 1 to 8)).
However, as a result of committed research by the inventors, the following new points have become clear.
Device Characteristic Depreciation
In JP-A-2002-231968 and JP-A-2012-38810, it is possible to form a p-n junction portion of a p-type inversion region and an n− type drift layer in the vicinity of a surface of the n− type drift layer by platinum diffusion, and in JP-A-2012-38810 it is possible to improve the stability of forming the p-type inversion region by platinum diffusion by the introduction of point defects, but it is not possible to greatly change the platinum diffusion itself in the n− type drift layer. Because of this, the junction depth of the p-n junction portion of the p-type inversion region and n− type drift layer is shallow at about 1 μm to 3 μm from the n− type drift layer surface.
The junction depth of the p-n junction portion of the p-type inversion region and n− type drift layer is relatively determined by the donor concentration of the n− type drift layer and the acceptor concentration in the vicinity of the surface of the n− type drift layer compensated by the platinum acceptor. Because of this, it is possible to increase the junction depth of the p-n junction portion of the p-type inversion region and n− type drift layer by increasing the compensation by the platinum acceptor or reducing the donor concentration of the n− type drift layer.
For example, by raising the platinum diffusion temperature, it is possible to increase the compensation by the platinum acceptor in the vicinity of the surface of the n− type drift layer. However, the donor concentration other than in the vicinity of the surface of the n− type drift layer is also compensated by the platinum acceptor, and a problem occurs in that the lifetime of the whole of the n− type drift layer decreases, and the on-state voltage (forward voltage VF) increases. Also, when reducing the donor concentration of the n− type drift layer, a problem occurs in that reverse surge withstand capability decreases, and the like. Also, it is unrealistic in terms of diode manufacture to reduce the donor concentration by as large an extent to which the compensation by the platinum acceptor changes.
As above, it is difficult to increase the junction depth of the p-n junction portion of the p-type inversion region and n− type drift layer. However, when the element characteristics are adversely affected by damage (wire bonding damage) received from the chip surface when assembling or by impurities or moisture diffused from the chip surface, there is a demand for the device characteristics to be stabilized by the p-n junction portion of the p-type inversion region and n− type drift layer being a deep junction.
Device Breakdown Voltage Variation
Also, in JP-A-2012-38810, the curvature of the end portion of the p-type inversion region is increased, and stabilization of breakdown voltage is achieved, by controlling the intake of platinum into the oxide film. However, the junction depth of the p-n junction portion of the p-type inversion region and n− type drift layer being small, and the p-type inversion region formation in the oxide film aperture portion depending on the controllability of the intake of platinum into the oxide film, are essentially causes of variation in the end portion form of the p-type inversion region.
The curvature radius of the end portion of the p-type inversion region resulting from compensation by the platinum acceptor is extremely small in comparison with the curvature radius of the end portion of the p-type inversion region formed by a thermal diffusion of a p-type impurity such as boron. As a result of this, there is a problem in that the electrical field intensity of the end portion of a p-type anode region formed of the p-type inversion region increases easily when there is reverse bias, the device breakdown voltage decreases, and the leakage current is unstable.
Deterioration of Trade-Off Between Forward Voltage VF and Reverse Recovery Current IRP
Also, the diode indicated in JP-A-2002-231968 and JP-A-2012-38810 is such that there is concern that the trade-off between forward voltage VF and reverse recovery current IRP will deteriorate more than with a p-n junction diode formed of a p-type diffusion region fabricated to have the same breakdown voltage. It is assumed that this is due to the lifetime killer distribution of the platinum.
The lifetime killer distribution of the platinum is not sufficiently explained. This is because, for example, as the platinum detection sensitivity obtained from secondary ion mass spectroscopy (SIMS) is also high, in the vicinity of 1×1015 atoms/cm3, only the outermost platinum concentration distribution of the n− type drift layer is observed, and it is not possible to directly detect the platinum concentration distribution in the vicinity of the p-n junction portion, which affects device operation.
Therefore, the inventors have measured the resistivity distribution of the n− type drift layer after platinum diffusion, and estimated the lifetime killer distribution of the platinum by analogizing the platinum concentration distribution from the resistivity distribution. This is a method whereby the acceptor concentration distribution is estimated from the resistance change occurring when the impurity concentration of the n− type drift layer is compensated by platinum that has been formed into an acceptor, and the impurity concentration distribution of the platinum functioning as a lifetime killer is estimated from the acceptor concentration distribution. Results verifying this method of measuring platinum concentration distribution are shown in FIG. 17.
FIG. 17 is a characteristic diagram showing hole lifetime distribution in an n-type silicon layer. FIG. 17 is an n− type drift layer minority carrier (hole) lifetime distribution when assuming that the acceptor concentration distribution estimated from the resistivity change in the n− type drift layer occurring due to an eccentric location of platinum is equivalent to the platinum concentration distribution. Specifically, FIG. 17 shows the minority carrier (hole) lifetime distribution of a fast diode when the p-n junction portion is formed by platinum diffusion under general diffusion conditions (two hours at a temperature of 910° C.). As shown in FIG. 17, it is found that the resistivity change due to the eccentric location of platinum increases from a depth of in the region of 50 μm to 60 μm in the surface direction of the n− type drift layer.
When forming the p-n junction portion by platinum diffusion, the position of a p-n junction portion junction depth Xj and the position of an impurity concentration distribution change point A of the platinum functioning as a lifetime killer are far apart. Generally, a lifetime killer acts most efficiently in the vicinity of the p-n junction portion junction depth Xj, but being acted on in a portion deeper than the p-n junction portion junction depth Xj, and the lifetime being considerably reduced, is not desirable, as it leads to an increase in the forward voltage VF.
Consequently, as the lifetime distribution in the n− type drift layer differs with, for example, p-n junction portion junction depths Xj of 2 μm and 10 μm, the on-state voltage increases more when the p-n junction portion junction depth Xj is the shallower 2 μm. Meanwhile, it is assumed that the reverse recovery current IRP is smaller when the p-n junction portion junction depth Xj is the shallower 2 μm. However, the optimal p-n junction portion junction depth Xj (at which the VF-IRP trade-off is optimal) for the lifetime distribution is not clarified.
Normally, when forming the p-n junction portion by thermal diffusion of boron or the like, the p-n junction portion junction depth Xj can be variously changed in accordance with the boron dose and thermal diffusion conditions. However, when forming the p-n junction portion by platinum diffusion, controllability of the p-n junction portion junction depth Xj deteriorates, as it is limited by the concentration distribution of platinum eccentrically located at the surface of the n− type drift layer. A comparison will be made of the relationship between forward voltage and reverse recovery current between a diode formed of a p-type inversion region formed by a platinum acceptor and a normal p-n diode formed of a p-type diffusion region.
FIG. 18 is a characteristic diagram showing the relationship between forward voltage and reverse recovery current of heretofore known diodes. As shown in FIG. 18, it is clear that the trade-off characteristics of the forward voltage VF and reverse recovery current IRP of a diode formed of a p-type inversion region formed by a platinum acceptor are inferior in comparison with those of a normal p-n diode formed of a p-type diffusion region.
FIG. 18 shows diodes with a 400V breakdown voltage, wherein a forward current IF is taken to be 10 A and a current change rate di/dt is taken to be 100 A/μsec, but the kind of relationship between the forward voltage VF and reverse recovery current IRP shown in FIG. 18 appears more noticeably in a thick device with a breakdown voltage of 600V or more wherein the thickness of the n− type drift layer is more than the range of 50 μm to 60 μm, as heretofore described.
Also, in JP-A-2009-239269, JP-A-2003-282575, Japanese Patent No. 3,952,452, and JP-A-4-125933, there is a description of a method of controlling the platinum concentration distribution using vacancies or crystal defects of helium or the like, but there is no description of a p-n junction diode being formed by the action of advancing the formation of platinum into an acceptor, as there is in JP-A-2002-231968 and JP-A-2012-38810. That is, in JP-A-2009-239269, JP-A-2003-282575, Japanese Patent No. 3,952,452, and JP-A-4-125933, there is no description or hint as to whether or not the platinum acts as an acceptor, no mention of the impurity concentration distribution of platinum that has been formed into an acceptor, or of a method of controlling platinum acceptor concentration. Consequently, it is not possible in JP-A-2009-239269, JP-A-2003-282575, Japanese Patent No. 3,952,452, or JP-A-4-125933 to solve the problems that occur in JP-A-2002-231968 and JP-A-2012-38810.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.